Combinatorial optimization: algorithms and complexity
Combinatorial optimization: algorithms and complexity
Computer networks
Introduction to algorithms
High-level synthesis from VHDL with exact timing constraints
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
A tree-based scheduling algorithm for control-dominated circuits
DAC '93 Proceedings of the 30th international Design Automation Conference
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on low-power design
Scheduling of behavioral VHDL by retiming techniques
EURO-DAC '94 Proceedings of the conference on European design automation
Global scheduling with code-motions for high-level synthesis applications
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Behavioral synthesis methodology for HDL-based specification and validation
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
1995 high level synthesis design repository
ISSS '95 Proceedings of the 8th international symposium on System synthesis
An efficient graph algorithm for FSM scheduling
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Synthesis and Optimization of Digital Circuits
Synthesis and Optimization of Digital Circuits
High-Level Synthesis for Real-Time Digital Signal Processing
High-Level Synthesis for Real-Time Digital Signal Processing
Computers and Intractability: A Guide to the Theory of NP-Completeness
Computers and Intractability: A Guide to the Theory of NP-Completeness
A new symbolic technique for control-dependent scheduling
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
An efficient and versatile scheduling algorithm based on SDC formulation
Proceedings of the 43rd annual Design Automation Conference
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To adopt behavioral synthesis techniques in existing design flows, the synthesis methodology must provide the designer with a mechanism to specify a component's interface timing. This will permit pre- and postsynthesis validation through cosimulation with other subsystems or even through formal verification. In control-flow dominated designs, additional timing constraints will result in a complex specification/constraint system for which the scheduling problem has been shown to be NP-complete. In this article, we present a mathematical framework for solving a special instance of the scheduling problem in control-flow dominated behavioral VHDL descriptions given that the timing of I/O signals has been completely or partially specified. It is based on a code-transformation approach that fully preserves the VHDL semantics. The scheduling problem is mapped onto an integer linear program (ILP) solvable in polynomial time assuming a restricted partial order on selected statements. It captures both control-flow and timing constraints in a single model and also exploits dataflow information to optimize the statement sequence across basic block boundaries.