Three competing design methodologies for ASIC's: architectual synthesis, logic synthesis, logic synthesis and module generation

The FSM network model for behavioral synthesis of control-dominated machines

DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference

The Princeton University behavioral synthesis system

DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference

High-level synthesis from VHDL with exact timing constraints

DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference

An Automaton Model for Scheduling Constraints in Synchronous Machines

IEEE Transactions on Computers

A reuse scenario for the VHDL-based hardware design flow

EURO-DAC '95/EURO-VHDL '95 Proceedings of the conference on European design automation