Timing analysis in high-level synthesis
ICCAD '92 1992 IEEE/ACM international conference proceedings on Computer-aided design
The Princeton University behavioral synthesis system
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
High-level synthesis from VHDL with exact timing constraints
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Communications of the ACM
Switching and Finite Automata Theory: Computer Science Series
Switching and Finite Automata Theory: Computer Science Series
Logic Minimization Algorithms for VLSI Synthesis
Logic Minimization Algorithms for VLSI Synthesis
Sequential Circuit Design Using Synthesis and Optimization
ICCD '92 Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors
Algebraic structure theory of sequential machines (Prentice-Hall international series in applied mathematics)
High-level synthesis with distributed controller for fast timing closure
Proceedings of the International Conference on Computer-Aided Design
Critical-path-aware high-level synthesis with distributed controller for fast timing closure
ACM Transactions on Design Automation of Electronic Systems (TODAES)
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This paper describes new algorithms which combine state assignment and pipelining to perform timing-driven synthesis. A cycle time requirement for a controller-datapath system must be satisfied under fixed arrival times of datapath outputs and departure times of datapath inputs. As a result, the controller's design must take into account not only cycle time of the FSM in isolation, but also input arrival time specifications and output departure time requirements. Most state assignment methods minimize area; moreover, state assignment alone may not be sufficient to eliminate all delay bottlenecks. Performance-Driven Synthesis (PDS) applies both high-level and sequential optimizations to meet a cycle time requirement: we use new don't-care assignment algorithms to minimize the delays of FSM output signals on critical paths by reducing their dependencies on late-arriving FSM primary input signals; we also use new pipelining algoirithms to break critical paths which cannot be fixed by state assignment. Experimental results show that PDS improves delays with little area overhead.