Tutorial on high-level synthesis
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
Logic Minimization Algorithms for VLSI Synthesis
Logic Minimization Algorithms for VLSI Synthesis
Flexible timing specification in a VHDL synthesis subset
EURO-DAC '92 Proceedings of the conference on European design automation
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Previous data abstraction efforts in software and hardware description have approached abstract data types from a specification and simulation standpoint. This paper addresses the use of abstract data types for high-level synthesis. Data types are extended to support don't care information and new synthesis steps are presented. Results from a number of realistic design examples indicate that the area and delay of logic implementations can be substantially reduced when data abstraction and appropriate synthesis procedures are incorporated into the high-level synthesis process.