Interfacing incompatible protocols using interface process generation
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Automatic synthesis of interfaces between incompatible protocols
DAC '98 Proceedings of the 35th annual Design Automation Conference
Automated composition of hardware components
DAC '98 Proceedings of the 35th annual Design Automation Conference
Synthesizing Converters Between Finite State Protocols
ICCD '91 Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors
Convertibility verification and converter synthesis: two faces of the same coin
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Bridge Over Troubled Wrappers: Automated Interface Synthesis
VLSID '04 Proceedings of the 17th International Conference on VLSI Design
Proceedings of the conference on Design, automation and test in Europe - Volume 1
Protocol Transducer Synthesis using Divide and Conquer approach
ASP-DAC '07 Proceedings of the 2007 Asia and South Pacific Design Automation Conference
Provably correct on-chip communication: A formal approach to automatic protocol converter synthesis
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Formally Synthesising a Protocol Converter: A Case Study
CIAA '09 Proceedings of the 14th International Conference on Implementation and Application of Automata
Formal model of a protocol converter
CATS '09 Proceedings of the Fifteenth Australasian Symposium on Computing: The Australasian Theory - Volume 94
High-fidelity Markovian power model for protocols
Proceedings of the Conference on Design, Automation and Test in Europe
Multi-clock SoC design using protocol conversion
Proceedings of the Conference on Design, Automation and Test in Europe
A formal approach to design space exploration of protocol converters
Proceedings of the Conference on Design, Automation and Test in Europe
A halting algorithm to determine the existence of decoder
Proceedings of the 2010 Conference on Formal Methods in Computer-Aided Design
Inferring assertion for complementary synthesis
Proceedings of the International Conference on Computer-Aided Design
ACS: automatic converter synthesis for SoC bus protocols
TACAS'10 Proceedings of the 16th international conference on Tools and Algorithms for the Construction and Analysis of Systems
Correct-by-construction multi-component SoC design
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
| Hi-index | 0.00 |
In the absence of a single module interface standard, integration of pre-designed modules in System-on-Chip design often requires the use of protocol converters. Existing approaches to automatic synthesis of protocol converters mostly lack formal foundations and either employ abstractions that ignore crucial low level behaviors, or grossly simplify the structure of the protocols considered. We present a state-machine based formal model for bus based communication protocols, and precisely define protocol compatibility, and correct protocol conversion. Our model is expressive enough to capture features of commercial protocols such as bursts, pipelined transfers, wait state insertion, and data persistence, in cycle accurate detail. We show that the most general, correct converter for a pair of protocols, can be described as the greatest fixed point of a function for updating buffer states. This characterization yields a natural algorithm for automatic synthesis of a provably correct converter by iterative computation of the fixed point. We report our experience with automatic converter synthesis between widely used commercial bus protocols, such as AMBA AHB, ASB, APB, and OCP, considering features which are beyond the scope of current techniques.