ACS: automatic converter synthesis for SoC bus protocols

Authors:
Karin Avnit;Arcot Sowmya;Jorgen Peddersen
Affiliations:
The University of New South Wales, Sydney, Australia;The University of New South Wales, Sydney, Australia;The University of New South Wales, Sydney, Australia
Venue:
TACAS'10 Proceedings of the 16th international conference on Tools and Algorithms for the Construction and Analysis of Systems
Year:
2010

Citing 3
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Abstract

In System-on-Chip (SoC) design, pre-designed and pre- verified modules are often integrated into the system. In the absence of a single interface standard for such modules, “plug-n-play style” integration is not likely, as the modules are often designed to comply with different interface protocols, and a protocol converter is required to mediate between them. ACS is a tool that allows for automatic checking of protocol compatibility and automatic converter synthesis for SoC bus based protocols. It is based on formal foundations and guarantees correct-by-construction deterministic solutions in VHDL, whenever it is physically possible to mediate between a given pair of protocols.