Automatic synthesis of interfaces between incompatible protocols

  • Authors:
  • Roberto Passerone;James A. Rowson;Alberto Sangiovanni-Vincentelli

  • Affiliations:
  • Department of EECS, University of California at Berkeley;Alta Group of Cadence, Sunnyvale, California;Department of EECS, University of California at Berkeley

  • Venue:
  • DAC '98 Proceedings of the 35th annual Design Automation Conference
  • Year:
  • 1998

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Abstract

A t the system level, reusable Intellectual Property (or IP) blo cks can be represented abstractly as blocks that exchange messages. The concrete implementations of these IP blocks m ust exc hange the messages through complex signaling protocols. Interfacing bet ween IP that use different signaling protocols is a tedious and error prone design task. We propose using regular expression based protocol descriptions to sho w ho w to map the message on to a signaling protocol. Given t w o protocols,an algorithm is proposed to build an interface machine. We ha ve implemented our algorithm in a program named PIG that synthesizes a Verilog implementation based on a regular expression protocol description.