Interface timing verification with application to synthesis
DAC '94 Proceedings of the 31st annual Design Automation Conference
Efficient algorithms for interface timing verification
EURO-DAC '94 Proceedings of the conference on European design automation
Modeling and synthesis of timed asynchronous circuits
EURO-DAC '94 Proceedings of the conference on European design automation
Interfacing incompatible protocols using interface process generation
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Min-max linear programming and the timing analysis of digital circuits
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Asynchronous interface specification, analysis and synthesis
DAC '98 Proceedings of the 35th annual Design Automation Conference
Automatic synthesis of interfaces between incompatible protocols
DAC '98 Proceedings of the 35th annual Design Automation Conference
Introduction to Algorithms
Synthesis and Optimization of Combinational Interface Circuits
Journal of VLSI Signal Processing Systems
Synthesizing Converters Between Finite State Protocols
ICCD '91 Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors
Algorithms for Interface Timing Verification
ICCD '92 Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors
ICCD '00 Proceedings of the 2000 IEEE International Conference on Computer Design: VLSI in Computers & Processors
Bridge Over Troubled Wrappers: Automated Interface Synthesis
VLSID '04 Proceedings of the 17th International Conference on VLSI Design
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Most of the Intellectual Properties (IPs) of the System-on-Chip (SoC) are provided by different vendors such that they can have various characteristics. It makes that the interface circuit synthesis of the SoC is a time-consuming and error-prone design. In the past, some heuristic algorithms have been proposed for the interface circuit design of the System-on-Chip (SoC) but none of them can generate optimal solutions. The main contribution of this paper is to present an optimal interface synthesis algorithm for power optimization in interface circuit design of the SoC. Experiment results demonstrates the effectiveness of our algorithms.