Synthesis and Optimization of Combinational Interface Circuits

  • Authors:
  • Ki-Seok Chung;Rajesh K. Gupta;Taewhan Kim;C. L. Liu

  • Affiliations:
  • Department of Computer Engineering, Hongik University, Seoul, Korea;Department of Information and Computer Science, University of California, Irvine, CA 92697, USA;Department of Electrical Engineering & Computer Science and Advanced Information Technology Research Center (AITrc), Korea Advanced Institute of Science and Technology, Daejon, Korea;Department of Computer Science, Tsing Hua University, Hsinchu, Taiwan ROC

  • Venue:
  • Journal of VLSI Signal Processing Systems
  • Year:
  • 2002

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Abstract

We describe an algorithm for interface synthesis and optimization for embedded system components such as microprocessors, memory ASIC, and network subsystems. The algorithm accepts the timing characteristics of two chips as input, and generates a combinational interface circuitry to implement communication between them. The algorithm consists of two parts. In the first part, we determine the direct pin-to-pin connections employing a 0-1 ILP formulation to minimize wiring area and dynamic power consumption in the resulting interface circuit. In the second part, we use a novel encoding method to synthesize connections between chips which require additional gates in the interface circuit. Experiments show that our algorithm is very effective in practice.