Automatic synthesis of interfaces between incompatible protocols
DAC '98 Proceedings of the 35th annual Design Automation Conference
Protocol Transducer Synthesis using Divide and Conquer approach
ASP-DAC '07 Proceedings of the 2007 Asia and South Pacific Design Automation Conference
A Post-Silicon Debug Support Using High-Level Design Description
ATS '09 Proceedings of the 2009 Asian Test Symposium
Transaction-based debugging of system-on-chips with patterns
ICCD'09 Proceedings of the 2009 IEEE international conference on Computer design
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In general on-chip communication protocols, such as OCP[1], can be specified and represented with finite state machines (FSM). Such communication protocols are basically collections of individual transactions or commands, such as simple read/write and bust read/write, and each transaction or command can be specified with a FSM. So a given communication protocol can be represented with a set of FSMs which work jointly. Based on these FSM-based specifications, we have been developing not only pure formal and semi-formal verification techniques using FSMs as specifications, but also synthesis and debugging techniques, such as automatic generation of protocol converters and post-silicon verification/ debugging supports. In this paper, we show first how FSM-based specifications can describe sate-of-the-art on-chip communication protocols, and then their application to such synthesis and verification/debug for SoC designs are presented.