Compilers: principles, techniques, and tools
Compilers: principles, techniques, and tools
Static scheduling of synchronous data flow programs for digital signal processing
IEEE Transactions on Computers
A system for compiling and debugging structured data processing controllers
EURO-DAC '96/EURO-VHDL '96 Proceedings of the conference on European design automation
Automatic synthesis of interfaces between incompatible protocols
DAC '98 Proceedings of the 35th annual Design Automation Conference
An MPEG-2 decoder case study as a driver for a system level design methodology
CODES '99 Proceedings of the seventh international workshop on Hardware/software codesign
Grammar-based hardware synthesis from port-size independent specifications
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
YAPI: application modeling for signal processing systems
Proceedings of the 37th Annual Design Automation Conference
System Design with SystemC
Formal Models for Embedded System Design
IEEE Design & Test
An Approach for Quantitative Analysis of Application-Specific Dataflow Architectures
ASAP '97 Proceedings of the IEEE International Conference on Application-Specific Systems, Architectures and Processors
A Network on Chip Architecture and Design Methodology
ISVLSI '02 Proceedings of the IEEE Computer Society Annual Symposium on VLSI
System-level design: orthogonalization of concerns and platform-based design
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
System-level performance analysis for designing on-chip communication architectures
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
System design for DSP applications in transaction level modeling paradigm
Proceedings of the 41st annual Design Automation Conference
A formal method for hardware IP design and integration under I/O and timing constraints
ACM Transactions on Embedded Computing Systems (TECS)
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Expensive top-down iterations are often required in the design cycle of complex DSP systems. In this paper, we introduce two levels of abstraction in the design flow by systematically categorizing the architectural decisions. As a result, the top-down iteration loop is broken. We also present a technique to capture and inject the architectural decisions such that the system models can be created and simulated efficiently. The concepts are illustrated by a realistic speech processing example, which is implemented using the AMBA on-chip architecture. Our methodology offers a smooth path from the functional modeling phase to the implementation level, facilitates the reuse of HW and SW components, and enjoys existing tool support at thebackend.