Reachability analysis using partitioned-ROBDDs

  • Authors:

  • Amit Narayan;Adrian J. Isles;Jawahar Jain;Robert K. Brayton;Alberto L. Sangiovanni-Vincentelli

  • Affiliations:

  • Department of Electrical Engineering and Computer Sciences, University of California, Berkeley, CA;Department of Electrical Engineering and Computer Sciences, University of California, Berkeley, CA;Fujitsu Laboratories of America, Santa Clara, CA;Department of Electrical Engineering and Computer Sciences, University of California, Berkeley, CA;Department of Electrical Engineering and Computer Sciences, University of California, Berkeley, CA

  • Venue:
  • ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
  • Year:
  • 1997

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Abstract

In this paper, we address the problem of finite state machine (FSM) traversal, a key step in most sequential verification and synthesis algorithms. We propose the use of partitioned-ROBDDs to reduce the memory explosion problem associated with symbolic state space exploration techniques. In our technique, the reachable state set is represented as a partitioned-ROBDD Different partitions of the Boolean space are allowed to have different variable orderings and only one partition needs to be in memory at any given time. We show the effectiveness of our approach on a set of ISCAS89 benchmark circuits. Our techniques result in a significant reduction in total memory utilization. For a given memory limit, partitioned-ROBDD based method can complete traversal for many circuits for which monolithic ROBDDs fail. For circuits where both partitioned-ROBDDs as well as monolithic-ROBDDs cannot complete traversal, partitioned-ROBDDs can reach a significantly larger set of states.