A new reachability algorithm for symmetric multi-processor architecture

Authors:
Debashis Sahoo;Jawahar Jain;Subramanian Iyer;David Dill
Affiliations:
Stanford University, Stanford, CA;Fujitsu Labs of America;University of Texas at Austin, Austin, TX;Stanford University, Stanford, CA
Venue:
ATVA'05 Proceedings of the Third international conference on Automated Technology for Verification and Analysis
Year:
2005

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Abstract

Partitioned BDD-based algorithms have been proposed in the literature to solve the memory explosion problem in BDD-based verification. A naive parallelization of such algorithms is often ineffective as they have less parallelism. In this paper we present a novel parallel reachability approach that lead to a significantly faster verification on a Symmetric Multi-Processing architecture over the existing one-thread, one-CPU approaches. We identify the issues and bottlenecks in parallelizing BDD-based reachability algorithm. We show that in most cases our algorithm achieves good speedup compared to the existing sequential approaches.