Graph-Based Algorithms for Boolean Function Manipulation
IEEE Transactions on Computers
Efficient implementation of a BDD package
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
Breadth-first manipulation of SBDD of Boolean functions for vector processing
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
The Stanford Dash Multiprocessor
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Efficient breadth-first manipulation of binary decision diagrams
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
DAC '94 Proceedings of the 31st annual Design Automation Conference
High performance BDD package by exploiting memory hierarchy
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Implementation of an efficient parallel BDD package
DAC '96 Proceedings of the 33rd annual Design Automation Conference
ACV: an arithmetic circuit verifier
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
MORE: an alternative implementation of BDD packages by multi-operand synthesis
EURO-DAC '96/EURO-VHDL '96 Proceedings of the conference on European design automation
Dynamic variable ordering for ordered binary decision diagrams
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Breadth-first manipulation of very large binary-decision diagrams
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
A new model for integrated nested task and data parallel programming
PPOPP '97 Proceedings of the sixth ACM SIGPLAN symposium on Principles and practice of parallel programming
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ICCD '96 Proceedings of the 1996 International Conference on Computer Design, VLSI in Computers and Processors
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FMCAD '96 Proceedings of the First International Conference on Formal Methods in Computer-Aided Design
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EDTC '96 Proceedings of the 1996 European conference on Design and Test
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FRONTIERS '95 Proceedings of the Fifth Symposium on the Frontiers of Massively Parallel Computation (Frontiers'95)
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ICCD '97 Proceedings of the 1997 International Conference on Computer Design (ICCD '97)
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SC '98 Proceedings of the 1998 ACM/IEEE conference on Supercomputing
Proceedings of the 42nd annual Design Automation Conference
Under-approximation Heuristics for Grid-based Bounded Model Checking
Electronic Notes in Theoretical Computer Science (ENTCS)
Electronic Notes in Theoretical Computer Science (ENTCS)
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ICATPN'00 Proceedings of the 21st international conference on Application and theory of petri nets
Parallel disk-based computation for large, monolithic binary decision diagrams
Proceedings of the 4th International Workshop on Parallel and Symbolic Computation
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IPDPS'06 Proceedings of the 20th international conference on Parallel and distributed processing
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ATVA'05 Proceedings of the Third international conference on Automated Technology for Verification and Analysis
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ACM Transactions on Design Automation of Electronic Systems (TODAES)
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Electronic Notes in Theoretical Computer Science (ENTCS)
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With the increasing complexity of protocol and circuit designs, formal verification has become an important research area and binary decision diagrams (BDDs) have been shown to be a powerful tool in formal verification. This paper presents a parallel algorithm for BDD construction targeted at shared memory multiprocessors and distributed shared memory systems. This algorithm focuses on improving memory access locality through specialized memory managers and partial breadth-first expansion, and on improving processor utilization through dynamic load balancing. The results on a shared memory system show speedups of over two on four processors and speedups of up to four on eight processors. The measured results clearly identify the main source of bottlenecks and point out some intereeting directions for further improvements.