Graph-Based Algorithms for Boolean Function Manipulation
IEEE Transactions on Computers
Verification of synchronous sequential machines based on symbolic execution
Proceedings of the international workshop on Automatic verification methods for finite state systems
Efficient implementation of a BDD package
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
Sequential circuit verification using symbolic model checking
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
Algorithms for approximate FSM traversal
DAC '93 Proceedings of the 30th international Design Automation Conference
High-density reachability analysis
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
DAC '97 Proceedings of the 34th annual Design Automation Conference
Reachability analysis using partitioned-ROBDDs
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Improving symbolic traversals by means of activity profiles
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
A Performance Study of BDD-Based Model Checking
FMCAD '98 Proceedings of the Second International Conference on Formal Methods in Computer-Aided Design
Biasing symbolic search by means of dynamic activity profiles
Proceedings of the conference on Design, automation and test in Europe
Application of linearly transformed BDDs in sequential verification
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
A 3-step approach for performance-driven whole-chip routing
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
| Hi-index | 0.03 |
Symbolic techniques have revolutionized reachability analysis in the last years. Extending their applicability to handle large, industrial designs is a key issue, involving the need to focus on memory consumption for BDD representation as well as time consumption to perform symbolic traversals of Finite State Machines (FSMs). We address the problem of reachability analysis for large FSMs, introducing a novel technique that performs reachability analysis using a sequence of “distance driven” partial traversals based on dynamically chosen prunings of the transition relation. Experiments are given to demonstrate the efficiency and robustness of our approach: We succeed in completing reachability problems with significantly smaller memory requirements and improved time performance.