Graph-Based Algorithms for Boolean Function Manipulation
IEEE Transactions on Computers
Representing circuits more efficiently in symbolic model checking
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Computer-aided verification of coordinating processes: the automata-theoretic approach
Computer-aided verification of coordinating processes: the automata-theoretic approach
Model checking, abstraction, and compositional verification
Model checking, abstraction, and compositional verification
High-density reachability analysis
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Tearing based automatic abstraction for CTL model checking
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Improved reachability analysis of large finite state machines
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Dynamic variable ordering for ordered binary decision diagrams
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Safe BDD minimization using don't cares
DAC '97 Proceedings of the 34th annual Design Automation Conference
Formal verification in a commercial setting
DAC '97 Proceedings of the 34th annual Design Automation Conference
DAC '97 Proceedings of the 34th annual Design Automation Conference
Reachability analysis using partitioned-ROBDDs
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Efficient Model Checking by Automated Ordering of Transition Relation Partitions
CAV '94 Proceedings of the 6th International Conference on Computer Aided Verification
A Conjunctively Decomposed Boolean Representation for Symbolic Model Checking
CAV '96 Proceedings of the 8th International Conference on Computer Aided Verification
VIS: A System for Verification and Synthesis
CAV '96 Proceedings of the 8th International Conference on Computer Aided Verification
Automatic Abstraction Techniques for Propositional µ-calculus Model Checking
CAV '97 Proceedings of the 9th International Conference on Computer Aided Verification
Formal analysis of synchronous circuits
Formal analysis of synchronous circuits
Algorithms for approximate FSM traversal based on state space decomposition
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Verification by approximate forward and backward reachability
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Polynomial methods for allocating complex components
DATE '99 Proceedings of the conference on Design, automation and test in Europe
Improving symbolic traversals by means of activity profiles
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Iterative abstraction-based CTL model checking
DATE '00 Proceedings of the conference on Design, automation and test in Europe
Polynomial circuit models for component matching in high-level synthesis
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - System Level Design
Ordered binary decision diagrams as knowledge-bases
Artificial Intelligence
SIVA: A System for Coverage-Directed State Space Search
Journal of Electronic Testing: Theory and Applications
Comparing Symbolic and Explicit Model Checking of a Software System
Proceedings of the 9th International SPIN Workshop on Model Checking of Software
Multiple State and Single State Tableaux for Combining Local and Global Model Checking
Correct System Design, Recent Insight and Advances, (to Hans Langmaack on the occasion of his retirement from his professorship at the University of Kiel)
Symbolic Simulation with Approximate Values
FMCAD '00 Proceedings of the Third International Conference on Formal Methods in Computer-Aided Design
Hints to accelerate Symbolic Traversal
CHARME '99 Proceedings of the 10th IFIP WG 10.5 Advanced Research Working Conference on Correct Hardware Design and Verification Methods
Implicit test generation for behavioral VHDL models
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Utilizing don't care states in SAT-based bounded sequential problems
GLSVLSI '05 Proceedings of the 15th ACM Great Lakes symposium on VLSI
Fast falsification based on symbolic bounded property checking
Proceedings of the 43rd annual Design Automation Conference
Decomposing image computation for symbolic reachability analysis using control flow information
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Inferring Congruence Equations Using SAT
CAV '08 Proceedings of the 20th international conference on Computer Aided Verification
Approximate Compilation of Constraints into Multivalued Decision Diagrams
CP '08 Proceedings of the 14th international conference on Principles and Practice of Constraint Programming
Bit-precise reasoning with affine functions
SMT '08/BPR '08 Proceedings of the Joint Workshops of the 6th International Workshop on Satisfiability Modulo Theories and 1st International Workshop on Bit-Precise Reasoning
Distributed Symbolic Bounded Property Checking
Electronic Notes in Theoretical Computer Science (ENTCS)
Variable-latency design by function speculation
Proceedings of the Conference on Design, Automation and Test in Europe
Verifying very large industrial circuits using 100 processes and beyond
ATVA'05 Proceedings of the Third international conference on Automated Technology for Verification and Analysis
Widening ROBDDs with prime implicants
TACAS'06 Proceedings of the 12th international conference on Tools and Algorithms for the Construction and Analysis of Systems
Approximating checkers for simulation acceleration
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
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Efficient techniques for the manipulation of Binary Decision Diagrams (BDDs) are key to the success of formal verification tools. Recent advances in reachability analysis and model checking algorithms have emphasized the need for efficient algorithms for the approximation and decomposition of BDDs. In this paper we present a new algorithm for approximation and analyze its performance in comparison with existing techniques. We also introduce a new decomposition algorithm that produces balanced partitions. The effectiveness of our contributions is demonstrated by improved results in reachability analysis for some hard problem instances.