Graph-Based Algorithms for Boolean Function Manipulation
IEEE Transactions on Computers
Verification of synchronous sequential machines based on symbolic execution
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DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
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DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
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ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
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IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Approximation and decomposition of binary decision diagrams
DAC '98 Proceedings of the 35th annual Design Automation Conference
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DAC '98 Proceedings of the 35th annual Design Automation Conference
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DATE '99 Proceedings of the conference on Design, automation and test in Europe
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DATE '99 Proceedings of the conference on Design, automation and test in Europe
DATE '00 Proceedings of the conference on Design, automation and test in Europe
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CAV '02 Proceedings of the 14th International Conference on Computer Aided Verification
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HLDVT '03 Proceedings of the Eighth IEEE International Workshop on High-Level Design Validation and Test Workshop
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Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Don't care words with an application to the automata-based approach for real addition
Formal Methods in System Design
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
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Proceedings of the Conference on Design, Automation and Test in Europe
Don't care words with an application to the automata-based approach for real addition
CAV'06 Proceedings of the 18th international conference on Computer Aided Verification
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CHARME'05 Proceedings of the 13 IFIP WG 10.5 international conference on Correct Hardware Design and Verification Methods
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In many computer-aided design tools, binary decision diagrams(BDDs) are used to represent Boolean functions. To increase theefficiency and capability of these tools, many algorithms have beendeveloped to reduce the size of BDDs. This paper presents heuristicalgorithms that minimize the size of BDDs representing incompletelyspecified functions by intelligently assigning don't cares tobinary values. The traditional algorithm, restrict [Verification of Synchronous Sequential Machines Based on Symbolic Execution], is often effectivein BDD minimization, but can increase the BDD size. We proposenew algorithms based on restrict which are guaranteed neverto increase the size of the BDD, thereby significantly reducing peakmemory requirements. Experimental results show that our techniquestypically yield significantly smaller BDDs than restrict.