Fast falsification based on symbolic bounded property checking

Authors:
Prakash M. Peranandam;Pradeep K. Nalla;Jürgen Ruf;Roland J. Weiss;Thomas Kropf;Wolfgang Rosenstiel
Affiliations:
University of Tübingen, Germany;University of Tübingen, Germany;University of Tübingen, Germany;University of Tübingen, Germany;University of Tübingen, Germany;University of Tübingen, Germany
Venue:
Proceedings of the 43rd annual Design Automation Conference
Year:
2006

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Abstract

Symbolic property verification is an increasingly popular debugging method based on Binary Decision Diagrams (BDDs). The lack of optimization of the state space search is often responsible for the excessive growth of the BDDs. In this paper we present an accelerated symbolic property verification by means of a new guiding technique that automatically finds the set of interesting variables by exploiting the property and the transition relation of a design. Our property based state space guiding can substantially speed up the verification process. The heuristic picks up the interesting state or the input variables automatically and utilizes them in guiding the state space traversal. This guiding approach is a novel one as it is automatic, efficient and stable for fast falsification. Furthermore it does not degrade as much for full validation.