Model checking, abstraction, and compositional verification
Model checking, abstraction, and compositional verification
Efficient generation of counterexamples and witnesses in symbolic model checking
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
RuleBase: an industry-oriented formal verification tool
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Improved reachability analysis of large finite state machines
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Reachability analysis using partitioned-ROBDDs
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Symbolic Model Checking
On-the-Fly Model Checking of RCTL Formulas
CAV '98 Proceedings of the 10th International Conference on Computer Aided Verification
Achieving Scalability in Parallel Reachability Analysis of Very Large Circuits
CAV '00 Proceedings of the 12th International Conference on Computer Aided Verification
Parallelizing the Murphi Verifier
CAV '97 Proceedings of the 9th International Conference on Computer Aided Verification
Efficient On-the-Fly Model Checking for CTL
LICS '95 Proceedings of the 10th Annual IEEE Symposium on Logic in Computer Science
Distributed LTL model-checking in SPIN
SPIN '01 Proceedings of the 8th international SPIN workshop on Model checking of software
Formal Methods in System Design
Distributed LTL Model Checking Based on Negative Cycle Detection
FST TCS '01 Proceedings of the 21st Conference on Foundations of Software Technology and Theoretical Computer Science
Distributed Symbolic Model Checking for µ-Calculus
CAV '01 Proceedings of the 13th International Conference on Computer Aided Verification
Symmetry in temporal logic model checking
ACM Computing Surveys (CSUR)
Fast falsification based on symbolic bounded property checking
Proceedings of the 43rd annual Design Automation Conference
CTL* model checking on a shared-memory architecture
Formal Methods in System Design
Dealing with practical limitations of distributed timed model checking for timed automata
Formal Methods in System Design
How to Order Vertices for Distributed LTL Model-Checking Based on Accepting Predecessors
Electronic Notes in Theoretical Computer Science (ENTCS)
Distribution, Approximation and Probabilistic Model Checking
Electronic Notes in Theoretical Computer Science (ENTCS)
Distributed explicit fair cycle detection: set based approach
SPIN'03 Proceedings of the 10th international conference on Model checking software
A case study in domain-customized model checking for real-time component software
ISoLA'04 Proceedings of the First international conference on Leveraging Applications of Formal Methods
Parallel external directed model checking with linear i/o
VMCAI'06 Proceedings of the 7th international conference on Verification, Model Checking, and Abstract Interpretation
Conditional model checking: a technique to pass information between verifiers
Proceedings of the ACM SIGSOFT 20th International Symposium on the Foundations of Software Engineering
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This paper presents a scalable method for parallel symbolic on-thefly model checking on a distributed-memory environment of workstations. Our method combines a parallel version of an on-the-fly model checker for safety properties with a scalable scheme for reachability analysis. The extra load of storage required for counter example generation is evenly distributed among the processes by our memory balancing. For the sake of scalability, at no point during computation the memory of a single process contains all the data from any of the cycles. The counter example generation is thus performed through collaboration of the parallel processes. We develop a method for the counter example generation keeping a low peak memory requirement during the backward step and the computation of the inverse transition relation.We implemented our method on a standard, loosely-connected environment of workstations, using a high-performance SMV-based model checker. Our initial performance evaluation using several large circuits shows that our method can check models that are too large to fit in the memory of a single node. Our on-thefly approach may find counter examples even when the model is too large to fit in the memory of the parallel system.