Symmetry in temporal logic model checking

  • Authors:
  • Alice Miller;Alastair Donaldson;Muffy Calder

  • Affiliations:
  • University of Glasgow, Glasgow, UK;University of Glasgow, Glasgow, UK;University of Glasgow, Glasgow, UK

  • Venue:
  • ACM Computing Surveys (CSUR)
  • Year:
  • 2006

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Abstract

Temporal logic model checking involves checking the state-space of a model of a system to determine whether errors can occur in the system. Often this involves checking symmetrically equivalent areas of the state-space. The use of symmetry reduction to increase the efficiency of model checking has inspired a wealth of activity in the area of model checking research. We provide a survey of the associated literature.