Graph-Based Algorithms for Boolean Function Manipulation
IEEE Transactions on Computers
Algorithms for scalable synchronization on shared-memory multiprocessors
ACM Transactions on Computer Systems (TOCS)
Better verification through symmetry
Formal Methods in System Design - Special issue on symmetry in automatic verification
Exploiting symmetry in temporal logic model checking
Formal Methods in System Design - Special issue on symmetry in automatic verification
Formal Methods in System Design - Special issue on symmetry in automatic verification
SMC: a symmetry-based model checker for verification of safety and liveness properties
ACM Transactions on Software Engineering and Methodology (TOSEM)
POPL '77 Proceedings of the 4th ACM SIGACT-SIGPLAN symposium on Principles of programming languages
Exploiting Symmetry when Model-Checking Software
FORTE XII / PSTV XIX '99 Proceedings of the IFIP TC6 WG6.1 Joint International Conference on Formal Description Techniques for Distributed Systems and Communication Protocols (FORTE XII) and Protocol Specification, Testing and Verification (PSTV XIX)
From Asymmetry to Full Symmetry: New Techniques for Symmetry Reduction in Model Checking
CHARME '99 Proceedings of the 10th IFIP WG 10.5 Advanced Research Working Conference on Correct Hardware Design and Verification Methods
Specification and verification of concurrent systems in CESAR
Proceedings of the 5th Colloquium on International Symposium on Programming
Liveness with (0, 1, infty)-Counter Abstraction
CAV '02 Proceedings of the 14th International Conference on Computer Aided Verification
Combining Symmetry Reduction and Under-Approximation for Symbolic Model Checking
CAV '02 Proceedings of the 14th International Conference on Computer Aided Verification
Design and Synthesis of Synchronization Skeletons Using Branching-Time Temporal Logic
Logic of Programs, Workshop
Exploiting symmetry when verifying transistor-level circuits by symbolic trajectory evaluation
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Symmetry in temporal logic model checking
ACM Computing Surveys (CSUR)
Computer Networks: The International Journal of Computer and Telecommunications Networking
Extending Symmetry Reduction Techniques to a Realistic Model of Computation
Electronic Notes in Theoretical Computer Science (ENTCS)
Model checking: algorithmic verification and debugging
Communications of the ACM - Scratch Programming for All
Electronic Notes in Theoretical Computer Science (ENTCS)
Sviss: symbolic verification of symmetric systems
TACAS'08/ETAPS'08 Proceedings of the Theory and practice of software, 14th international conference on Tools and algorithms for the construction and analysis of systems
On the constructive orbit problem
Annals of Mathematics and Artificial Intelligence
Families of Symmetries as Efficient Models of Resource Binding
Electronic Notes in Theoretical Computer Science (ENTCS)
Context-aware counter abstraction
Formal Methods in System Design
Model checking a model checker: a code contract combined approach
ICFEM'10 Proceedings of the 12th international conference on Formal engineering methods and software engineering
Symmetry reduction for probabilistic model checking
CAV'06 Proceedings of the 18th international conference on Computer Aided Verification
Systematic construction of abstractions for model-checking
VMCAI'06 Proceedings of the 7th international conference on Verification, Model Checking, and Abstract Interpretation
Exact and approximate strategies for symmetry reduction in model checking
FM'06 Proceedings of the 14th international conference on Formal Methods
Symmetry reduction for probabilistic model checking using generic representatives
ATVA'06 Proceedings of the 4th international conference on Automated Technology for Verification and Analysis
A computational group theoretic symmetry reduction package for the SPIN model checker
AMAST'06 Proceedings of the 11th international conference on Algebraic Methodology and Software Technology
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Symmetry reduction is a technique to combat the state explosion problem in temporal logic model checking. Its use with symbolic representation has suffered from the prohibitively large BDD for the orbit relation. One suggested solution is to pre-compute a mapping from states to possibly multiple representatives of symmetry equivalence classes. In this paper, we propose a more efficient method that determines representatives dynamically during fixpoint iterations. Our scheme preserves the uniqueness of representatives. Another alternative to using the orbit relation is counter abstraction. It proved efficient for the special case of full symmetry, provided a conducive program structure. In contrast, our solution applies also to systems with less than full symmetry, and to systems where a translation into counters is not feasible. We support these claims with experimental results.