The C programming language
Better verification through symmetry
Formal Methods in System Design - Special issue on symmetry in automatic verification
Exploiting symmetry in temporal logic model checking
Formal Methods in System Design - Special issue on symmetry in automatic verification
Formal Methods in System Design - Special issue on symmetry in automatic verification
Model checking
SMC: a symmetry-based model checker for verification of safety and liveness properties
ACM Transactions on Software Engineering and Methodology (TOSEM)
Symmetry Reductions inModel Checking
CAV '98 Proceedings of the 10th International Conference on Computer Aided Verification
Power Efficient Processor Architecture and The Cell Processor
HPCA '05 Proceedings of the 11th International Symposium on High-Performance Computer Architecture
Symmetry in temporal logic model checking
ACM Computing Surveys (CSUR)
Extending Symmetry Reduction Techniques to a Realistic Model of Computation
Electronic Notes in Theoretical Computer Science (ENTCS)
The Design of a Multicore Extension of the SPIN Model Checker
IEEE Transactions on Software Engineering
Spin model checker, the: primer and reference manual
Spin model checker, the: primer and reference manual
Automatic symmetry detection for model checking using computational group theory
FM'05 Proceedings of the 2005 international conference on Formal Methods
TACAS'05 Proceedings of the 11th international conference on Tools and Algorithms for the Construction and Analysis of Systems
Exact and approximate strategies for symmetry reduction in model checking
FM'06 Proceedings of the 14th international conference on Formal Methods
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Symmetry reduction is an effective state-space reduction technique for model checking, and works by restricting search to equivalence class representatives with respect to a group of symmetries for a model. A major problem with symmetry reduction techniques is the time taken to compute the representative of a state, which can be prohibitive. In efficient implementations of symmetry reduction, a symmetry is applied to a state as a sequence of operations which swap component identities. We show that vector processing technology, common to modern computers, can be used to implement a vectorised swap operation, which can be incorporated into the representative computation algorithm to accelerate symmetry reduction. Via a worked example, we present details of this vector symmetry reduction method. We have implemented our techniques in the TopSpin symmetry reduction package for the Spin model checker, and present experimental results showing the speedups obtained via vectorisation for two case-studies running on a PowerPC vector processor.