Exploiting symmetry in temporal logic model checking
Formal Methods in System Design - Special issue on symmetry in automatic verification
SMC: a symmetry-based model checker for verification of safety and liveness properties
ACM Transactions on Software Engineering and Methodology (TOSEM)
IEEE Transactions on Software Engineering
Combining symmetry reduction and under-approximation for symbolic model checking
Formal Methods in System Design
Model checking concurrent linux device drivers
Proceedings of the twenty-second IEEE/ACM international conference on Automated software engineering
Reducing model checking of the few to the one
ICFEM'06 Proceedings of the 8th international conference on Formal Methods and Software Engineering
TACAS'05 Proceedings of the 11th international conference on Tools and Algorithms for the Construction and Analysis of Systems
Extending Symmetry Reduction by Exploiting System Architecture
VMCAI '09 Proceedings of the 10th International Conference on Verification, Model Checking, and Abstract Interpretation
Symbolic Counter Abstraction for Concurrent Software
CAV '09 Proceedings of the 21st International Conference on Computer Aided Verification
Context-aware counter abstraction
Formal Methods in System Design
| Hi-index | 0.00 |
SVISS is a flexible platform for incorporating efficient symmetry reduction into symbolic model checking. The tool comes with an extensive C++ library for system modeling using BDDs and a rich CTLbased model checking engine. Applications range from communication protocols to computer hardware and multi-threaded software. We believe Sviss to be the first symbolic tool to exploit symmetry in concurrent device-driver verification, which is vital in operating system design.