Automatic verification of finite-state concurrent systems using temporal logic specifications
ACM Transactions on Programming Languages and Systems (TOPLAS)
Handbook of theoretical computer science (vol. B)
Computer-aided verification of coordinating processes: the automata-theoretic approach
Computer-aided verification of coordinating processes: the automata-theoretic approach
Formal Methods in System Design - Special issue on symmetry in automatic verification
Utilizing symmetry when model-checking under fairness assumptions: an automata-theoretic approach
ACM Transactions on Programming Languages and Systems (TOPLAS)
Modalities for model checking (extended abstract): branching time strikes back
POPL '85 Proceedings of the 12th ACM SIGACT-SIGPLAN symposium on Principles of programming languages
On-the-Fly Model Checking Under Fairness that Exploits Symmetry
Formal Methods in System Design
SMC: a symmetry-based model checker for verification of safety and liveness properties
ACM Transactions on Software Engineering and Methodology (TOSEM)
Exploiting Symmetry when Model-Checking Software
FORTE XII / PSTV XIX '99 Proceedings of the IFIP TC6 WG6.1 Joint International Conference on Formal Description Techniques for Distributed Systems and Communication Protocols (FORTE XII) and Protocol Specification, Testing and Verification (PSTV XIX)
Exploiting Symmetry In Temporal Logic Model Checking
CAV '93 Proceedings of the 5th International Conference on Computer Aided Verification
Better Verification Through Symmetry
CHDL '93 Proceedings of the 11th IFIP WG10.2 International Conference sponsored by IFIP WG10.2 and in cooperation with IEEE COMPSOC on Computer Hardware Description Languages and their Applications
LICS '00 Proceedings of the 15th Annual IEEE Symposium on Logic in Computer Science
Symmetry in temporal logic model checking
ACM Computing Surveys (CSUR)
Checking extended CTL properties using guarded quotient structures
Formal Methods in System Design
Extending Symmetry Reduction by Exploiting System Architecture
VMCAI '09 Proceedings of the 10th International Conference on Verification, Model Checking, and Abstract Interpretation
Role-Based Symmetry Reduction of Fault-Tolerant Distributed Protocols with Language Support
ICFEM '09 Proceedings of the 11th International Conference on Formal Engineering Methods: Formal Methods and Software Engineering
CAV'07 Proceedings of the 19th international conference on Computer aided verification
Depth bounded explicit-state model checking
Proceedings of the 18th international SPIN conference on Model checking software
Exploring structural symmetry automatically in symbolic trajectory evaluation
Formal Methods in System Design
Automatic symmetry detection for model checking using computational group theory
FM'05 Proceedings of the 2005 international conference on Formal Methods
VMCAI'06 Proceedings of the 7th international conference on Verification, Model Checking, and Abstract Interpretation
Symmetry reduction for b by permutation flooding
B'07 Proceedings of the 7th international conference on Formal Specification and Development in B
A complete method for symmetry reduction in safety verification
CAV'12 Proceedings of the 24th international conference on Computer Aided Verification
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Symmetry reduction methods exploit symmetry in a system in order to efficiently verify its temporal properties. Two problems may prevent the use of symmetry reduction in practice: (1) the property to be checked may distinguish symmetric states and hence not be preserved by the symmetry, and (2) the system may exhibit little or no symmetry. In this article, we present a general framework that addresses both of these problems. We introduce "Guarded Annotated Quotient Structures" for compactly representing the state space of systems even when those are asymmetric. We then present algorithms for checking any temporal property on such representations, including non-symmetric properties.