Formal verification by symbolic evaluation of partially-ordered trajectories
Formal Methods in System Design - Special issue on symbolic model checking
Better verification through symmetry
Formal Methods in System Design - Special issue on symmetry in automatic verification
Exploiting symmetry in temporal logic model checking
Formal Methods in System Design - Special issue on symmetry in automatic verification
ML for the working programmer (2nd ed.)
ML for the working programmer (2nd ed.)
Formal verification of content addressable memories using symbolic trajectory evaluation
DAC '97 Proceedings of the 34th annual Design Automation Conference
Combining theorem proving and trajectory evaluation in an industrial environment
DAC '98 Proceedings of the 35th annual Design Automation Conference
A methodology for hardware verification using compositional model checking
Science of Computer Programming - Special issue on mathematics of program construction
Structural Symmetry and Model Checking
CAV '98 Proceedings of the 10th International Conference on Computer Aided Verification
VIS: A System for Verification and Synthesis
CAV '96 Proceedings of the 8th International Conference on Computer Aided Verification
Formal verification of memory arrays
Formal verification of memory arrays
Introduction to generalized symbolic trajectory evaluation
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on the 2001 international conference on computer design (ICCD)
Symmetry and reduced symmetry in model checking
ACM Transactions on Programming Languages and Systems (TOPLAS)
Automatic Abstraction in Symbolic Trajectory Evaluation
FMCAD '07 Proceedings of the Formal Methods in Computer Aided Design
Automatic refinement and vacuity detection for symbolic trajectory evaluation
CAV'06 Proceedings of the 18th international conference on Computer Aided Verification
An industrially effective environment for formal hardware verification
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A simple theorem prover based on symbolic trajectory evaluation and BDD's
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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This paper presents a formal theory to characterize symmetry in netlists and symmetry in properties. The inherent correlation between the two types of symmetry is formalized as a theorem, which provides the soundness of our symmetry reduction method. A practical tactic is introduced to effectively integrate the symmetry reduction approach in a hybrid verification environment which combines theorem proving and symbolic trajectory evaluation. Finally, the effecitveness of the symmetry reduction method is demonstrated by case studies.