An industrially effective environment for formal hardware verification

  • Authors:
  • C. -J.H. Seger;R. B. Jones;J. W. O'Leary;T. Melham;M. D. Aagaard;C. Barrett;D. Syme

  • Affiliations:
  • Strategic CAD Labs, Intel Corp., Hillsboro, OR, USA;-;-;-;-;-;-

  • Venue:
  • IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
  • Year:
  • 2006

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Abstract

The Forte formal verification environment for datapath-dominated hardware is described. Forte has proven to be effective in large-scale industrial trials and combines an efficient linear-time logic model-checking algorithm, namely the symbolic trajectory evaluation (STE), with lightweight theorem proving in higher-order logic. These are tightly integrated in a general-purpose functional programming language, which both allows the system to be easily customized and at the same time serves as a specification language. The design philosophy behind Forte is presented and the elements of the verification methodology that make it effective in practice are also described.