Formal verification using parametric representations of Boolean constraints
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
FMCAD '00 Proceedings of the Third International Conference on Formal Methods in Computer-Aided Design
Verification of Floating-Point Adders
CAV '98 Proceedings of the 10th International Conference on Computer Aided Verification
Automatic Formal Verification of Fused-Multiply-Add FPUs
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
Proceedings of the Eighth International Workshop on the ACL2 Theorem Prover and its Applications
Challenges for formal verification in industrial setting
FMICS'06/PDMC'06 Proceedings of the 11th international workshop, FMICS 2006 and 5th international workshop, PDMC conference on Formal methods: Applications and technology
Floating-Point verification using theorem proving
SFM'06 Proceedings of the 6th international conference on Formal Methods for the Design of Computer, Communication, and Software Systems
An industrially effective environment for formal hardware verification
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Verifying VIA Nano microprocessor components
Proceedings of the 2010 Conference on Formal Methods in Computer-Aided Design
A monadic approach to automated reasoning for Bluespec SystemVerilog
Innovations in Systems and Software Engineering
A trustworthy monadic formalization of the ARMv7 instruction set architecture
ITP'10 Proceedings of the First international conference on Interactive Theorem Proving
A mechanically verified AIG-to-BDD conversion algorithm
ITP'10 Proceedings of the First international conference on Interactive Theorem Proving
RockSalt: better, faster, stronger SFI for the x86
Proceedings of the 33rd ACM SIGPLAN conference on Programming Language Design and Implementation
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We have verified floating-point addition/subtraction instructions for the media unit from Centaur's 64-bit, X86-compatible microprocessor. This unit implements over one hundred instructions, with the most complex being floating-point addition/subtraction. This media unit can add/subtract four pairs of floating-point numbers every clock cycle with an industry-leading two-cycle latency. Using the ACL2 theorem proving system, we model the media unit by translating its Verilog design into an HDL that we have deeply embedded in the ACL2 logic. We specify the addition/subtraction instructions as integer-based ACL2 functions. Using a combination of AIG- and BDD-based symbolic simulation, case splitting, and theorem proving, we produce a mechanically checked theorem in ACL2 for each instruction examined stating that the hardware model yields the same result as the instruction specification. In pursuit of these verifications, we implemented a formal HDL and symbolic simulation framework, including formally verified BDD and AIG operators, within the ACL2 theorem proving system. The HDL includes an extensible interpreter capable of performing concrete and symbolic simulations as well as non-functional analyses. We know of no other symbolic simulation-based floating-point verification that is performed within a single formal system and produces a theorem in that system without relying on unverified external tools.