A Mechanically Checked Proof of the AMD5K86TM Floating-Point Division Program
IEEE Transactions on Computers
RTL verification: a floating-point multiplier
Computer-Aided reasoning
Computer-Aided Reasoning: An Approach
Computer-Aided Reasoning: An Approach
A Mechanically Checked Proof of Correctness of the AMD K5 Floating Point Square Root Microcode
Formal Methods in System Design
The SNAP Project: Design of Floating Point Arithmetic Units
ARITH '97 Proceedings of the 13th Symposium on Computer Arithmetic (ARITH '97)
Formal Verification of the VAMP Floating Point Unit
CHARME '01 Proceedings of the 11th IFIP WG 10.5 Advanced Research Working Conference on Correct Hardware Design and Verification Methods
Formal Verification Methods for Industrial Hardware Design
SOFSEM '01 Proceedings of the 28th Conference on Current Trends in Theory and Practice of Informatics Piestany: Theory and Practice of Informatics
Formalization of Cadence SPW Fixed-Point Arithmetic in HOL
IFM '02 Proceedings of the Third International Conference on Integrated Formal Methods
Automatic Formal Verification of Fused-Multiply-Add FPUs
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
Formal Verification of the VAMP Floating Point Unit
Formal Methods in System Design
Challenges in the Formal Verification of Complete State-of-the-Art Processors
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
Provably faithful evaluation of polynomials
Proceedings of the 2006 ACM symposium on Applied computing
Formalization of fixed-point arithmetic in HOL
Formal Methods in System Design
Getting Formal Verification into Design Flow
FM '08 Proceedings of the 15th international symposium on Formal Methods
Centaur Technology Media Unit Verification
CAV '09 Proceedings of the 21st International Conference on Computer Aided Verification
Challenges for formal verification in industrial setting
FMICS'06/PDMC'06 Proceedings of the 11th international workshop, FMICS 2006 and 5th international workshop, PDMC conference on Formal methods: Applications and technology
Verifying VIA Nano microprocessor components
Proceedings of the 2010 Conference on Formal Methods in Computer-Aided Design
A monadic approach to automated reasoning for Bluespec SystemVerilog
Innovations in Systems and Software Engineering
Component reuse in b using ACL2
ZB'05 Proceedings of the 4th international conference on Formal Specification and Development in Z and B
| Hi-index | 0.00 |
One obstacle to mathematical verification of industrial hard-ware designs is that the commercial hardware description languages in which they are usually encoded are too complicated and poorly specified to be readily susceptible to formal analysis. As an alternative to these commercial languages, AMD has developed an RTL language for microprocessor designs that is simple enough to admit a clear semantic definition, providing a basis for formal verification. We describe a mechanical proof system for designs represented in this language, consisting of a translator to the ACL2 logical programming language and a methodology for verifiying properties of the resulting programs using the ACL2 prover. As an illustration, we present a proof of IEEE compliance of the floating-point adder of the AMD Athlon processor.