Formal Methods Applied to a Floating-Point Number System
IEEE Transactions on Software Engineering
IEEE Transactions on Computers
How to read floating point numbers accurately
PLDI '90 Proceedings of the ACM SIGPLAN 1990 conference on Programming language design and implementation
A proof of the nonrestoring division algorithm and its implementation on an ALU
Formal Methods in System Design - Special issue on designing correct circuits
The formal verification of a pipelined double-precision IEEE floating-point multiplier
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Bit-level analysis of an SRT divider circuit
DAC '96 Proceedings of the 33rd annual Design Automation Conference
ACV: an arithmetic circuit verifier
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Computer architecture (2nd ed.): a quantitative approach
Computer architecture (2nd ed.): a quantitative approach
A Mechanically Checked Proof of the AMD5K86TM Floating-Point Division Program
IEEE Transactions on Computers
Formal verification of iterative algorithms in microprocessors
Proceedings of the 37th Annual Design Automation Conference
Computer Architecture: Complexity and Correctness
Computer Architecture: Complexity and Correctness
A Mechanically Checked Proof of Correctness of the AMD K5 Floating Point Square Root Microcode
Formal Methods in System Design
Floating Point Verification in HOL Light: The Exponential Function
AMAST '97 Proceedings of the 6th International Conference on Algebraic Methodology and Software Technology
Verification of IEEE Compliant Subtractive Division Algorithms
FMCAD '96 Proceedings of the First International Conference on Formal Methods in Computer-Aided Design
Verification of All Circuits in a Floating-Point Unit Using Word-Level Model Checking
FMCAD '96 Proceedings of the First International Conference on Formal Methods in Computer-Aided Design
FMCAD '00 Proceedings of the Third International Conference on Formal Methods in Computer-Aided Design
Mechanizing Verification of Arithmetic Circuits: SRT Division
Proceedings of the 17th Conference on Foundations of Software Technology and Theoretical Computer Science
Verification of Floating-Point Adders
CAV '98 Proceedings of the 10th International Conference on Computer Aided Verification
CAV '02 Proceedings of the 14th International Conference on Computer Aided Verification
Modular Verification of SRT Division
CAV '96 Proceedings of the 8th International Conference on Computer Aided Verification
Verifying the SRT Division Algorithm Using Theorem Proving Techniques
CAV '96 Proceedings of the 8th International Conference on Computer Aided Verification
PVS: A Prototype Verification System
CADE-11 Proceedings of the 11th International Conference on Automated Deduction: Automated Deduction
On the Design of IEEE Compliant Floating Point Units
ARITH '97 Proceedings of the 13th Symposium on Computer Arithmetic (ARITH '97)
Formal Verification of the Pentium® 4 Floating-Point Multiplier
Proceedings of the conference on Design, automation and test in Europe
Defining the IEEE-854 Floating-Point Standard in PVS
Defining the IEEE-854 Floating-Point Standard in PVS
FPGA paranoia: testing numerical properties of FPGA floating point IP-Cores
ARC'12 Proceedings of the 8th international conference on Reconfigurable Computing: architectures, tools and applications
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We report on the formal verification of the floating point unit used in the VAMP processor. The dual-precision FPU is IEEE compliant and supports denormals and exceptions in hardware. The supported operations are addition, subtraction, multiplication, division, comparison, and conversions.We have formalized the IEEE standard 754. The formalization is supplemented by a rich theory of rounding, which includes notations and theorems facilitating the verification of the actual hardware. The theory of rounding enables the separation of the hardware into smaller modules which can be verified individually. Each module is verified on the gate level against a formal specification. The combination of these formal specifications, together with the theorems from the theory of rounding, yield the overall correctness of the FPU, i.e., theorems stating that the gate-level hardware complies with the high-level formalization of the IEEE standard. The verification is done completely in the theorem prover PVS.We further report on the implementation and test of the verified FPU on a Xilinx FPGA.