RTL verification: a floating-point multiplier

A Case Study in Fomal Verification of Register-Transfer Logic with ACL2: The Floating Point Adder of the AMD AthlonTM Processor

FMCAD '00 Proceedings of the Third International Conference on Formal Methods in Computer-Aided Design

Partial Functions in ACL2

Journal of Automated Reasoning

Verification of executable pipelined machines with bit-level interfaces

ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design

Efficient execution in an automated reasoning environment

Journal of Functional Programming

The Challenge of Hardware-Software Co-verification

Verified Software: Theories, Tools, Experiments

Challenges for formal verification in industrial setting

FMICS'06/PDMC'06 Proceedings of the 11th international workshop, FMICS 2006 and 5th international workshop, PDMC conference on Formal methods: Applications and technology

Code-based test generation for validation of functional processor descriptions

TACAS'03 Proceedings of the 9th international conference on Tools and algorithms for the construction and analysis of systems

Refinement and theorem proving

SFM'06 Proceedings of the 6th international conference on Formal Methods for the Design of Computer, Communication, and Software Systems