Code-based test generation for validation of functional processor descriptions

Authors:
Fabrice Baray;Philippe Codognet;Daniel Diaz;Henri Michel
Affiliations:
ST-Microelectronics, Central R&D, France and University of Paris 6, LIP6, France;University of Paris 6, LIP6, France;University of Paris 1, France;ST-Microelectronics, Central R&D, France
Venue:
TACAS'03 Proceedings of the 9th international conference on Tools and algorithms for the construction and analysis of systems
Year:
2003

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Abstract

Microprocessor design deals with many types of specifications: from functional models (SystemC or proprietary languages) to hardware description languages such as VHDL or Verilog. Functional descriptions are key to the development of new processors or System On Chips at ST Micro electronics. In this paper we address the problem of automatic generation of high quality test-suites for microprocessor functional models validation. We present the design and implementation of a software tool based on constraint solving techniques which analyzes the control flow of the initial description in order to generate tests for each path. The test vectors are computed with a dedicated constraint solver designed to handle specific constraints related to typical constructs found in microprocessor descriptions. Results are illustrated with a case study.