IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Chaff: engineering an efficient SAT solver
Proceedings of the 38th annual Design Automation Conference
POPL '77 Proceedings of the 4th ACM SIGACT-SIGPLAN symposium on Principles of programming languages
Symbolic Model Checking without BDDs
TACAS '99 Proceedings of the 5th International Conference on Tools and Algorithms for Construction and Analysis of Systems
Functional Test Generation using Constraint Logic Programming
VLSI-SOC '01 Proceedings of the IFIP TC10/WG10.5 Eleventh International Conference on Very Large Scale Integration of Systems-on/Chip: SOC Design Methodologies
Constraint Processing
Functional Verification for SystemC Descriptions Using Constraint Solving
Proceedings of the conference on Design, automation and test in Europe
EXE: automatically generating inputs of death
Proceedings of the 13th ACM conference on Computer and communications security
Constraint Logic Programming using Eclipse
Constraint Logic Programming using Eclipse
Structural Testing of Executables
ICST '08 Proceedings of the 2008 International Conference on Software Testing, Verification, and Validation
Global difference constraint propagation for finite domain solvers
Proceedings of the 10th international ACM SIGPLAN conference on Principles and practice of declarative programming
Decision Procedures: An Algorithmic Point of View
Decision Procedures: An Algorithmic Point of View
CAV '08 Proceedings of the 20th international conference on Computer Aided Verification
Boolector: An Efficient SMT Solver for Bit-Vectors and Arrays
TACAS '09 Proceedings of the 15th International Conference on Tools and Algorithms for the Construction and Analysis of Systems: Held as Part of the Joint European Conferences on Theory and Practice of Software, ETAPS 2009,
Test Selection Strategies for Lustre Descriptions in GATeL
Electronic Notes in Theoretical Computer Science (ENTCS)
Code-based test generation for validation of functional processor descriptions
TACAS'03 Proceedings of the 9th international conference on Tools and algorithms for the construction and analysis of systems
Efficient circuit to CNF conversion
SAT'07 Proceedings of the 10th international conference on Theory and applications of satisfiability testing
A decision procedure for bit-vectors and arrays
CAV'07 Proceedings of the 19th international conference on Computer aided verification
Interval analysis of microcontroller code using abstract interpretation of hardware and software
Proceedings of the 13th International Workshop on Software & Compilers for Embedded Systems
FDCC: a combined approach for solving constraints over finite domains and arrays
CPAIOR'12 Proceedings of the 9th international conference on Integration of AI and OR Techniques in Constraint Programming for Combinatorial Optimization Problems
Constraint satisfaction over bit-vectors
CP'12 Proceedings of the 18th international conference on Principles and Practice of Constraint Programming
Behind the scenes in SANTE: a combination of static and dynamic analyses
Automated Software Engineering
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The theory BV of bit-vectors, i.e. fixed-size arrays of bits equipped with standard low-level machine instructions, is becoming very popular in formal verification. Standard solvers for this theory are based on a bit-level encoding into propositional logic and SAT-based resolution techniques. In this paper, we investigate an alternative approach based on a word-level encoding into bounded arithmetic and Constraint Logic Programming (CLP) resolution techniques. We define an original CLP framework (domains and propagators) dedicated to bit-vector constraints. This framework is implemented in a prototype and thorough experimental studies have been conducted. The new approach is shown to perform much better than standard CLP-based approaches, and to considerably reduce the gap with the best SAT-based BV solvers.