Efficient translation of boolean formulas to CNF in formal verification of microprocessors
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Automatic memory reductions for RTL model verification
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Clause form conversions for boolean circuits
SAT'04 Proceedings of the 7th international conference on Theory and Applications of Satisfiability Testing
Effective preprocessing in SAT through variable and clause elimination
SAT'05 Proceedings of the 8th international conference on Theory and Applications of Satisfiability Testing
A fast linear-arithmetic solver for DPLL(T)
CAV'06 Proceedings of the 18th international conference on Computer Aided Verification
On SAT modulo theories and optimization problems
SAT'06 Proceedings of the 9th international conference on Theory and Applications of Satisfiability Testing
A refinement-based compositional reasoning framework for pipelined machine verification
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Automated deduction for verification
ACM Computing Surveys (CSUR)
BAT: the bit-level analysis tool
CAV'07 Proceedings of the 19th international conference on Computer aided verification
Faster SAT solving with better CNF generation
Proceedings of the Conference on Design, Automation and Test in Europe
Automated design debugging with maximum satisfiability
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A single-instance incremental SAT formulation of proof- and counterexample-based abstraction
Proceedings of the 2010 Conference on Formal Methods in Computer-Aided Design
An alternative to SAT-Based approaches for bit-vectors
TACAS'10 Proceedings of the 16th international conference on Tools and Algorithms for the Construction and Analysis of Systems
TACAS'10 Proceedings of the 16th international conference on Tools and Algorithms for the Construction and Analysis of Systems
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Modern SAT solvers are proficient at solving Boolean satisfiability problems in Conjunctive Normal Form (CNF). However, these problems mostly arise from general Boolean circuits that are then translated to CNF. We outline a simple and expressive data structure for describing arbitrary circuits, as well as an algorithm for converting circuits to CNF. Our experimental results over a large benchmark suite show that the CNF problems we generate are consistently smaller and more quickly solved by modern SAT solvers than the CNF problems generated by current CNF generation methods.