Functional Test Generation using Constraint Logic Programming

Fault Models and Test Generation for Hardware-Software Covalidation

IEEE Design & Test

Arithmetic Reasoning in DPLL-Based SAT Solving

Proceedings of the conference on Design, automation and test in Europe - Volume 1

Assertion-based automated functional vectors generation using constraint logic programming

Proceedings of the 14th ACM Great Lakes symposium on VLSI

Normalization at the arithmetic bit level

Proceedings of the 42nd annual Design Automation Conference

B-Cubing: New Possibilities for Efficient SAT-Solving

IEEE Transactions on Computers

Code-coverage guided prioritized test generation

Information and Software Technology

An alternative to SAT-Based approaches for bit-vectors

TACAS'10 Proceedings of the 16th international conference on Tools and Algorithms for the Construction and Analysis of Systems

Constraint satisfaction over bit-vectors

CP'12 Proceedings of the 18th international conference on Principles and Practice of Constraint Programming