SystemC
An automatic testbench generation tool for a SystemC functional verification methodology
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This paper addresses the problem of test vectors generationstarting from an high level description of the systemunder test, specified in SystemC. The verification methodconsidered is based upon the simulation of input sequences.The system model adopted is the classical Finite State Machinemodel. Then, according to different strategies, a setof sequences can be obtained, where a sequence is an orderedset of transitions. For each of these sequences, a setof constraints is extracted. Test sequences can be obtainedby generating and solving the constraints, by using a constraintsolver (GProlog). A solution of the constraint solveryields the values of the input signals for which a sequenceof transitions in the FSM is executed. If the constraints cannotbe solved, it implies that the corresponding sequencecannot be executed by any test. The presented algorithm isnot based on a specific fault model, but aims at reaching thehighest possible path coverage.