Assertion checking by combined word-level ATPG and modular arithmetic constraint-solving techniques
Proceedings of the 37th Annual Design Automation Conference
An RTL Abstraction Technique for Processor MicroarchitectureValidation and Test Generation
Journal of Electronic Testing: Theory and Applications - Special issue on microprocessor test and verification
Verification Simulation Acceleration UsingCode-Perturbation
Journal of Electronic Testing: Theory and Applications - Special issue on microprocessor test and verification
A VHDL error simulator for functional test generation
DATE '00 Proceedings of the conference on Design, automation and test in Europe
LPSAT: a unified approach to RTL satisfiability
Proceedings of the conference on Design, automation and test in Europe
Functional test generation for behaviorally sequential models
Proceedings of the conference on Design, automation and test in Europe
Fast sequential circuit test generation using high-level and gate-level techniques
Proceedings of the conference on Design, automation and test in Europe
SystemC: a homogenous environment to test embedded systems
Proceedings of the ninth international symposium on Hardware/software codesign
Coverage Metrics for Functional Validation of Hardware Designs
IEEE Design & Test
Verification of Processor Microarchitectures
VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium
A Domain Coverage Metric for the Validation of Behavioral VHDL Descriptions
ITC '00 Proceedings of the 2000 IEEE International Test Conference
EXPLOITING DON'T CARES TO ENHANCE FUNCTIONAL TESTS
ITC '00 Proceedings of the 2000 IEEE International Test Conference
A Validation Fault Model for Timing-Induced Functional Errors
ITC '01 Proceedings of the 2001 IEEE International Test Conference
SystemC
Fault Models and Test Generation for Hardware-Software Covalidation
IEEE Design & Test
Assertion-based automated functional vectors generation using constraint logic programming
Proceedings of the 14th ACM Great Lakes symposium on VLSI
Functional test generation based on word-level SAT
Journal of Systems Architecture: the EUROMICRO Journal
An efficient control-oriented coverage metric
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
A framework for the functional verification of systemC models
International Journal of Parallel Programming
Automatic constraint based test generation for behavioral HDL models
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Code-based test generation for validation of functional processor descriptions
TACAS'03 Proceedings of the 9th international conference on Tools and algorithms for the construction and analysis of systems
The shall-prototype-test development model
ECBS'97 Proceedings of the 1997 international conference on Engineering of computer-based systems
RUBASTEM: a method for testing VHDL behavioral models
HASE'04 Proceedings of the Eighth IEEE international conference on High assurance systems engineering
Journal of Electronic Testing: Theory and Applications
An alternative to SAT-Based approaches for bit-vectors
TACAS'10 Proceedings of the 16th international conference on Tools and Algorithms for the Construction and Analysis of Systems
Constraint satisfaction over bit-vectors
CP'12 Proceedings of the 18th international conference on Principles and Practice of Constraint Programming
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A method for generation of design verification tests from behavior-level VHDL programs is presented. The method generates stimuli to execute desired control-flow paths in the given VHDL program. This method is based on path enumeration, constraint generation and constraint solving techniques that have been traditionally used for software testing. Behavioral VHDL programs contain multiple communicating processes, signal assignment statements, and wait statements which are not found in traditional software programming languages. Our model of constraint generation is specifically developed for VHDL programs with such constructs. Control-flow paths for which design verification tests are desired are specified through certain annotations attached to the control statements in the VHDL programs. These annotations are used to enumerate the desired paths. Each enumerated path is translated into a set of mathematical constraints corresponding to the statements in the path. Methods for generating constraint variables corresponding to various types of carriers in VHDL and for mapping various VHDL statements into mathematical relationships among these constraint variables are developed. These methods treat spatial and temporal incarnations of VHDL carriers as unique constraint variables thereby preserving the semantics of the behavioral VHDL programs. Constraints are generated in the constraint programming language CLP(R) and are solved using the CLP(R) system. A solution to the set of constraints so generated yields a design verification test sequence which can be applied for executing the corresponding control path when the design is simulated. If no solution exists, then it implies that the corresponding path can never be executed. Experimental studies pertaining to the quality of path coverage and fault coverage of the verification tests are presented.