A VHDL error simulator for functional test generation

Verification of synchronous sequential machines based on symbolic execution

Proceedings of the international workshop on Automatic verification methods for finite state systems

Generation of design verification tests from behavioral VHDL programs using path enumeration and constraint programming

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Automatic generation of functional vectors using the extended finite state machine model

ACM Transactions on Design Automation of Electronic Systems (TODAES)

VHDL fault simulation for defect-oriented test and diagnosis of digital ICs

EURO-DAC '96/EURO-VHDL '96 Proceedings of the conference on European design automation

A fault model for VHDL descriptions at the register transfer level

EURO-DAC '96/EURO-VHDL '96 Proceedings of the conference on European design automation

Functional vector generation for HDL models using linear programming and 3-satisfiability

DAC '98 Proceedings of the 35th annual Design Automation Conference

The Verilog hardware description language (4th ed.)

The Verilog hardware description language (4th ed.)

Simulation vector generation from HDL descriptions for observability-enhanced statement coverage

Proceedings of the 36th annual ACM/IEEE Design Automation Conference

Fast sequential circuit test generation using high-level and gate-level techniques

Proceedings of the conference on Design, automation and test in Europe

Art of Software Testing

Art of Software Testing

Implicit test generation for behavioral VHDL models

ITC '98 Proceedings of the 1998 IEEE International Test Conference