Selecting Software Test Data Using Data Flow Information
IEEE Transactions on Software Engineering
A Test Design Methodology for Protocol Testing
IEEE Transactions on Software Engineering
An introduction to Estelle: a specification language for distributed systems
Computer Networks and ISDN Systems - Special Issue: Protocol Specification and Testing
Symbolic execution systems—a review
Software Engineering Journal
A Formal Evaluation of Data Flow Path Selection Criteria
IEEE Transactions on Software Engineering
Introduction to algorithms
A VHDL primer
Conformance testing methodologies and architectures for OSI protocols
Conformance testing methodologies and architectures for OSI protocols
Automatic generation of functional vectors using the extended finite state machine model
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Automatic generation of extended UIO sequences for communication protocols in an EFSM model
IWPTS '94 7th IFIP WG 6.1 international workshop on Protocol test systems
On fault coverage of tests for finite state specifications
Computer Networks and ISDN Systems - Special issue on protocol testing
Dual-state augmentation for minimizing conformance test costs
Computer Networks and ISDN Systems
A VHDL error simulator for functional test generation
DATE '00 Proceedings of the conference on Design, automation and test in Europe
Fast sequential circuit test generation using high-level and gate-level techniques
Proceedings of the conference on Design, automation and test in Europe
The Designer's Guide to VHDL
Testing Finite-State Machines: State Identification and Verification
IEEE Transactions on Computers
IEEE Transactions on Software Engineering
A Test Derivation Method for Protocol Conformance Testing
Proceedings of the IFIP WG6.1 Seventh International Conference on Protocol Specification, Testing and Verification VII
Generating Conformance Test Sequences for Combined Control and Data Flow of Communication Protocols
Proceedings of the IFIP TC6/WG6.1 Twelth International Symposium on Protocol Specification, Testing and Verification XII
Generation of Feasible Test Sequences for EFSM Models
TestCom '00 Proceedings of the IFIP TC6/WG6.1 13th International Conference on Testing Communicating Systems: Tools and Techniques
Test Generation in the Presence of Conflicting Timers
TestCom '00 Proceedings of the IFIP TC6/WG6.1 13th International Conference on Testing Communicating Systems: Tools and Techniques
Timed Test Cases Generation Based on State Characterization Technique
RTSS '98 Proceedings of the IEEE Real-Time Systems Symposium
A two-level approach to automated conformance testing of VHDL designs
A two-level approach to automated conformance testing of VHDL designs
Feasible test generation by elimination of inconsistencies in efsm models of computer and communication systems
A technique to generate feasible tests for communications systems with multiple timers
IEEE/ACM Transactions on Networking (TON)
Evaluation of architectures for reliable server pooling in wired and wireless environments
IEEE Journal on Selected Areas in Communications
GECCO '05 Proceedings of the 7th annual conference on Genetic and evolutionary computation
Separating sequence overlap for automated test sequence generation
Automated Software Engineering
Synthesis of test purpose directed reactive planning tester for nondeterministic systems
Proceedings of the twenty-second IEEE/ACM international conference on Automated software engineering
Specification of Timed EFSM Fault Models in SDL
FORTE '07 Proceedings of the 27th IFIP WG 6.1 international conference on Formal Techniques for Networked and Distributed Systems
Using formal specifications to support testing
ACM Computing Surveys (CSUR)
Fault masking by multiple timing faults in timed EFSM models
Computer Networks: The International Journal of Computer and Telecommunications Networking
Using status messages in the distributed test architecture
Information and Software Technology
Estimating the feasibility of transition paths in extended finite state machines
Automated Software Engineering
Generation of executable test cases based on behavioral UML system models
Proceedings of the 5th Workshop on Automation of Software Test
Generating a checking sequence with a minimum number of reset transitions
Automated Software Engineering
Static- and dynamic consistency analysis of UML state chart models
MODELS'10 Proceedings of the 13th international conference on Model driven engineering languages and systems: Part I
Efficient Generation of Stimuli for Functional Verification by Backjumping Across Extended FSMs
Journal of Electronic Testing: Theory and Applications
Information and Software Technology
Test case automatic generation research based on AADL behavior annex
AICI'11 Proceedings of the Third international conference on Artificial intelligence and computational intelligence - Volume Part I
Analyzing the impact of protocol changes on tests
TestCom'06 Proceedings of the 18th IFIP TC6/WG6.1 international conference on Testing of Communicating Systems
Message confidentiality testing of security protocols: passive monitoring and active checking
TestCom'06 Proceedings of the 18th IFIP TC6/WG6.1 international conference on Testing of Communicating Systems
Regression test suite prioritization using system models
Software Testing, Verification & Reliability
Computers in Biology and Medicine
| Hi-index | 14.99 |
A formal description of an implementation under test (IUT), such as its VHDL behavior description, is required to automatically generate feasible test sequences for the IUT. Although finite-state machines (FSMs) can be used to describe the control structures of communication protocols, the data portion can only be modeled by extended finite-state machines (EFSMs). However, infeasible paths due to the conflicts among the condition and action variables of EFSMs complicate the test generation process. This paper introduces a method enabling the automatic generation of realizable test sequences from a class of EFSMs. Algorithms to detect and eliminate conflicts caused by the interdependencies among the variables of a class of EFSM models are presented. After all conflicts are eliminated from the EFSM graph, the existing FSM-based automated test generation methods can be used to generate feasible test sequences. Recently, these algorithms have been implemented as a software package called INDEEL. This methodology is applied to generate feasible tests for protocols such as ACA and MIL-STD 188-220. Current applications include IETF protocols and ASAP.