Formal verification in hardware design: a survey
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Test Generation with Inputs, Outputs, and Quiescence
TACAs '96 Proceedings of the Second International Workshop on Tools and Algorithms for Construction and Analysis of Systems
A Method Enabling Feasible Conformance Test Sequence Generation for EFSM Models
IEEE Transactions on Computers
DART: directed automated random testing
Proceedings of the 2005 ACM SIGPLAN conference on Programming language design and implementation
Compositional dynamic test generation
Proceedings of the 34th annual ACM SIGPLAN-SIGACT symposium on Principles of programming languages
Randomized directed testing (REDIRECT) for Simulink/Stateflow models
EMSOFT '08 Proceedings of the 8th ACM international conference on Embedded software
Test generation based on symbolic specifications
FATES'04 Proceedings of the 4th international conference on Formal Approaches to Software Testing
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The further automation of the test development process beyond the automatic execution of tests is an increasing challenge, because the development of new functionalities has a higher pace than the test development. The use of model based techniques combined with test generation methods enable a fast test definition while the test oracle is calculated automatically. The presented approach was implemented in a research prototype, which was used to generate test cases out of an UML state chart model describing the behavior of the system under test. The resulting test sequences were executed on a hardware in the loop (HiL) and showed its applicability in an industrial setting.