Efficiently computing static single assignment form and the control dependence graph
ACM Transactions on Programming Languages and Systems (TOPLAS)
High-level synthesis: introduction to chip and system design
High-level synthesis: introduction to chip and system design
Online minimization of transition systems (extended abstract)
STOC '92 Proceedings of the twenty-fourth annual ACM symposium on Theory of computing
Automatic generation of functional vectors using the extended finite state machine model
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Techniques for improving the efficiency of sequential circuit test generation
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Symbolic execution and program testing
Communications of the ACM
Chaff: engineering an efficient SAT solver
Proceedings of the 38th annual Design Automation Conference
Art of Software Testing
Expanding an Extended Finite State Machine to aid Testability
COMPSAC '02 Proceedings of the 26th International Computer Software and Applications Conference on Prolonging Software Life: Development and Redevelopment
Implicit test generation for behavioral VHDL models
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Artificial Intelligence: A Modern Approach
Artificial Intelligence: A Modern Approach
Functional Verification of System on Chips-Practices, Issues and Challenges
ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference
Effective Techniques for High-Level ATPG
ATS '01 Proceedings of the 10th Asian Test Symposium
Performance measurement and analysis of certain search algorithms.
Performance measurement and analysis of certain search algorithms.
ICCD '03 Proceedings of the 21st International Conference on Computer Design
A Method Enabling Feasible Conformance Test Sequence Generation for EFSM Models
IEEE Transactions on Computers
Efficient ATPG for Design Validation Based On Partitioned State Exploration Histories
VTS '04 Proceedings of the 22nd IEEE VLSI Test Symposium
Efficient Conflict-Based Learning in an RTL Circuit Constraint Solver
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
Design Validation of Behavioral VHDL Descriptions for Arbitrary Fault Models
ETS '05 Proceedings of the 10th IEEE European Symposium on Test
Genetic algorithms: the philosopher's stone or an effective solution for high-level TPG?
HLDVT '03 Proceedings of the Eighth IEEE International Workshop on High-Level Design Validation and Test Workshop
Improving Gate-Level ATPG by Traversing Concurrent EFSMs
VTS '06 Proceedings of the 24th IEEE VLSI Test Symposium
Functional verification based on the EFSM model
HLDVT '04 Proceedings of the High-Level Design Validation and Test Workshop, 2004. Ninth IEEE International
Decision Procedures: An Algorithmic Point of View
Decision Procedures: An Algorithmic Point of View
State Joining and Splitting for the Symbolic Execution of Binaries
Runtime Verification
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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Extended finite state machines (EFSMs) can be efficiently adopted to model the functionality of complex designs without incurring the state explosion problem typical of the more traditional FSMs. However, traversing an EFSM can be more difficult than an FSM because the guards of EFSM transitions involve both primary inputs and registers. This paper first analyzes the hardness of traversing an EFSM according to the characteristics of its transitions. Then, it presents a methodology to generate an EFSM which is easy to be traversed. Finally, it proposes a functional deterministic automatic test pattern generation (ATPG) approach that exploits such EFSMs for functional verification. In particular, the ATPG approach joins backjumping, learning, and constraint solving to (i) early identify possible symptoms of design errors by efficiently exploring the whole state space of the design under verification (DUV), and (ii) generate effective input sequences to be used in further verification steps which require to stimulate the DUV. The effectiveness of the proposed approach is confirmed in the experimental result section, where it is compared with both genetic and pseudo-deterministic techniques.