Design Validation of Behavioral VHDL Descriptions for Arbitrary Fault Models

Authors:
Fei Xin;Maciej Ciesielski;Ian G. Harris
Affiliations:
University of Massachusetts at Amherst;University of Massachusetts at Amherst;University of California at Irvine
Venue:
ETS '05 Proceedings of the 10th IEEE European Symposium on Test
Year:
2005

Citing 0
Cited 1

Efficient Generation of Stimuli for Functional Verification by Backjumping Across Extended FSMs

Journal of Electronic Testing: Theory and Applications

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Abstract

An unified gate-level fault model for interconnect opens and bridges is proposed. Defects are modeled as constrained multiple line stuck-at faults. A novel feature of the proposed fault model is its flexibility to accommodate increasing levels of accuracy. ...