High-level test synthesis with hierarchical test generation for delay-fault testability
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Coverage driven high-level test generation using a polynomial model of sequential circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Efficient Generation of Stimuli for Functional Verification by Backjumping Across Extended FSMs
Journal of Electronic Testing: Theory and Applications
| Hi-index | 0.00 |
In this paper, we present a satisfiability-based algorithm forautomatically generating test sequences that target gate-levelstuck-at faults in a circuit by using its register-transfer level(RTL)description. Our methodology exploits a popular, unified RTLcircuit representation, called assignment decision diagrams, forits analysis and justifies module-level pre-computed test vectorson this representation. Test generation proceeds by abstracting thecomponents in this unified representation using input/outputpropagation rules, so that any justification/propagation event canbe captured as a Boolean implication. Consequently, we reduce RTLtest generation to a satisfiability (SAT) instance that has asignificantly lower complexity than the equivalent problem at thegate-level. Using the state-of-the-art SAT solver ZCHAFF, we showthat our RTL test generator can outperform gate-level sequentialautomatic test pattern generation (ATPG) in terms of both faultcoverage and test generation time (two-to-three orders of magnitudespeed-up), in comparable test application times. Furthermore, weshow that in a bi-level testing scenario, in which RTL ATPG isfollowed bygate-level sequential ATPG on the remaining faults, weimprove the fault coverage even further, while maintaining a highspeed-up in test generation time (nearly 29X) over pure gate-levelsequential ATPG, at comparable test application times.