Fault masking by multiple timing faults in timed EFSM models

Authors:
Y. Wang;M. í. Uyar;S. S. Batth;M. A. Fecko
Affiliations:
The City College of the City University of New York, New York, NY 10016, USA;The City College of the City University of New York, New York, NY 10016, USA;The City College of the City University of New York, New York, NY 10016, USA;Applied Research Area at Telcordia Technologies Inc., Piscataway, NJ 08854, USA
Venue:
Computer Networks: The International Journal of Computer and Telecommunications Networking
Year:
2009

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Abstract

Detection of multiple timing faults is a challenging task because these faults, although may be detectable individually, can mask each other's faulty behavior, making a faulty implementation under test (IUT) indistinguishable from a non-faulty one during testing. This phenomenon, called fault masking, is formally defined in this paper. It is proven that graph augmentation algorithms proposed for timed Extended Finite State Machines (EFSMs) with multiple timers can detect pairwise occurrences of classes of timing faults in an IUT and, hence, detects fault masking.