Fault masking by multiple timing faults in timed EFSM models
Computer Networks: The International Journal of Computer and Telecommunications Networking
A Statistical Approach to Test Stochastic and Probabilistic Systems
ICFEM '09 Proceedings of the 11th International Conference on Formal Engineering Methods: Formal Methods and Software Engineering
Testing a probabilistic FSM using interval estimation
Computer Networks: The International Journal of Computer and Telecommunications Networking
Testing timed systems modeled by Stream X-machines
Software and Systems Modeling (SoSyM)
Formal passive testing of timed systems: theory and tools
Software Testing, Verification & Reliability
A formal framework to test soft and hard deadlines in timed systems
Software Testing, Verification & Reliability
| Hi-index | 14.98 |
A set of graph augmentation algorithms are introduced to model a class of timing faults in timed-EFSM models. It is shown that the test sequences generated based on our models can detect 1-clock and n-clock timing faults, and incorrect timer setting faults in an implementation under test (IUT). It is proven that the size of the augmented graph resulting from our augmentation algorithms is in the same order of magnitude as of the original specification.