Specification of Timed EFSM Fault Models in SDL

Authors:
S. S. Batth;E. R. Vieira;A. Cavalli;M. Ü. Uyar
Affiliations:
The City College and Graduate Center of the City University of New York, New York, NY 10016, USA;Laboratoire SAMOVAR (CNRS) and GET/INT Evry Cedex, France;Laboratoire SAMOVAR (CNRS) and GET/INT Evry Cedex, France;The City College and Graduate Center of the City University of New York, New York, NY 10016, USA
Venue:
FORTE '07 Proceedings of the 27th IFIP WG 6.1 international conference on Formal Techniques for Networked and Distributed Systems
Year:
2007

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Abstract

In this paper, we apply our timing fault modeling strategy to writing formal specifications for communication protocols. Using the formal language of Specification and Description Language (SDL), we specify the Controllerprocess of rail-road crossing system, a popular benchmark for real-time systems. Our extended finite state machine (EFSM) model has the capability of representing a class of timing faults, which otherwise may not be detected in an IUT. Hit-or-Jumpalgorithm is applied to the SDL specification based on our EFSM model to generate a test sequence that can detect these timing faults. This application of fault modeling into SDL specification ensures the synchronization among the timing constraints of different processes, and enables generation of portable test sequences since they can be easily represented in other formal notations such as TTCN or MSC.