Pattern generation for a deterministic BIST scheme
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
A VHDL error simulator for functional test generation
DATE '00 Proceedings of the conference on Design, automation and test in Europe
Implicit test generation for behavioral VHDL models
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Testability Alternatives Exploration through Functional Testing
VTS '00 Proceedings of the 18th IEEE VLSI Test Symposium
Gauss-elimination-based generation of multiple seed-polynomial pairs for LFSR
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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The identification of the most suited BIST architecture is one of the bottlenecks in the actual application of self-testing techniques. The aim of this paper is the investigation of possible relations between the behavioral level specification of the circuit, and the structural level, where BIST logic is inserted. We propose to use behavioral test patterns to guide the selection of the most appropriate BIST architecture with respect to the given application as a trade-off between fault coverage and area overhead. The correlation between the behavioral analysis and the actual fault coverage of the inserted BIST logic has been shown on a number of benchmarks.