Behavioral test generation for the selection of BIST Logic
Journal of Systems Architecture: the EUROMICRO Journal - Defect and fault tolerance in VLSI Systems
An Application of Genetic Algorithms and BDDs to Functional Testing
ICCD '00 Proceedings of the 2000 IEEE International Conference on Computer Design: VLSI in Computers & Processors
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The aim of this paper is to show the effectiveness of a high-level approach to testability analysis and test pattern generation, when analyzing different classes of architectures implementing the same specification. A unique test set is derived on the behavioral specification, based on a functional error model, which shows a high correlation with the single stuck-at gate-level fault model.Such a test set is then tailored to the particular gate-level implementation by transforming it into a specific test sequence, based on the scheduling adopted by the high-level synthesis. Experimental results show that the application of such test sequences allows to accurately evaluate the testability of the architecture in terms of gate-level fault coverage, in a fraction of the time required by a gate-level test pattern generator.