Design complexity measurement and testing
Communications of the ACM
Supercompilers for parallel and vector computers
Supercompilers for parallel and vector computers
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A Novel Approach to Random Pattern Testing of Sequential Circuits
IEEE Transactions on Computers
A Fault Injection Technique for VHDL Behavioral-Level Models
IEEE Design & Test
A Rule-Based Software Test Data Generator
IEEE Transactions on Knowledge and Data Engineering
Fast Antirandom (FAR) Test Generation
HASE '98 The 3rd IEEE International Symposium on High-Assurance Systems Engineering
Assessing Neural Networks as Guides for Testing Activities
METRICS '96 Proceedings of the 3rd International Symposium on Software Metrics: From Measurement to Empirical Results
A weighted random pattern test generation system
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Automatic test vector cultivation for sequential VLSI circuits using genetic algorithms
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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Verification of high-assurance system designs before they are fabricated on chips reduces time and money costs related to chip testing. Test benches, which are used in simulating and verifying VHDL designs, need to perform efficiently and effectively. Test automation through the automated generation of test patterns increases the efficiency and effectiveness of behavioral verification. We apply heuristic rules to generate test cases for VHDL behavioral designs. Their aim is to increase code coverage. They are based on control-flow and data-flow analysis. We applied the RUle-BAsed Software TEsting Method (RUBASTEM) to small, medium, and large examples. The results of RUBASTEM showed that this method achieves higher branch coverage.