Automatic verification of finite-state concurrent systems using temporal logic specifications
ACM Transactions on Programming Languages and Systems (TOPLAS)
Logic verification methodology for PowerPC microprocessors
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Test program generation for functional verification of PowerPC processors in IBM
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Symbolic Model Checking
Using Formal Verification/Analysis Methods on the Critical Path in System Design: A Case Study
Proceedings of the 7th International Conference on Computer Aided Verification
Formal verification of a PowerPC microprocessor
ICCD '95 Proceedings of the 1995 International Conference on Computer Design: VLSI in Computers and Processors
Virtual chip: making functional models work on real target systems
DAC '98 Proceedings of the 35th annual Design Automation Conference
A reconfigurable logic machine for fast event-driven simulation
DAC '98 Proceedings of the 35th annual Design Automation Conference
High-level design verification of microprocessors via error modeling
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Fast prototyping: a system design flow for fast design, prototyping and efficient IP reuse
CODES '99 Proceedings of the seventh international workshop on Hardware/software codesign
Functional verification methodology for microprocessors using the Genesys test-program generator
DATE '99 Proceedings of the conference on Design, automation and test in Europe
Fast prototyping: a system design flow applied to a complex system-on-chip multiprocessor design
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
A study in coverage-driven test generation
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Automatic Vector Generation Using Constraints and Biasing
Journal of Electronic Testing: Theory and Applications - Special issue on microprocessor test and verification
A transaction-based unified simulation/emulation architecture for functional verification
Proceedings of the 38th annual Design Automation Conference
Practical concurrent ASIC and system design and verification
EDTC '97 Proceedings of the 1997 European conference on Design and Test
A "Design for Verification" Methodology
ISQED '01 Proceedings of the 2nd International Symposium on Quality Electronic Design
Proceedings of the 41st annual Design Automation Conference
Fast co-verification of HDL models
Microelectronic Engineering
Proceedings of the conference on Design, automation and test in Europe
Code-based test generation for validation of functional processor descriptions
TACAS'03 Proceedings of the 9th international conference on Tools and algorithms for the construction and analysis of systems
A transaction-based unified architecture for simulation and emulation
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Using model-based test program generator for simulation validation
ICESS'04 Proceedings of the First international conference on Embedded Software and Systems
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