System design methodology of ultraSPARC-I
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Innovative verification strategy reduces design cycle time for high-end SPARC processor
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Hardware emulation for functional verification of K5
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Functional verification methodology for the PowerPC 604 microprocessor
DAC '96 Proceedings of the 33rd annual Design Automation Conference
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Functional verification methodology of Chameleon processor
DAC '96 Proceedings of the 33rd annual Design Automation Conference
A C-based RTL design verification methodology for complex microprocessor
DAC '97 Proceedings of the 34th annual Design Automation Conference
A transaction-based unified simulation/emulation architecture for functional verification
Proceedings of the 38th annual Design Automation Conference
Interface synthesis between software chip model and target board
Journal of Systems Architecture: the EUROMICRO Journal
ICCD '00 Proceedings of the 2000 IEEE International Conference on Computer Design: VLSI in Computers & Processors
Communication-efficient hardware acceleration for fast functional simulation
Proceedings of the 41st annual Design Automation Conference
Proceedings of the 41st annual Design Automation Conference
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
FEMU: a firmware-based emulation framework for SoC verification
CODES/ISSS '10 Proceedings of the eighth IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
A transaction-based unified architecture for simulation and emulation
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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As design complexity increases, functional verification becomes a crucial issue to ensure design correctness at an early design stage. Traditional methods for verifying functional designs are based on the HDL simulation, which is becoming the bottleneck of the design cycle because of the increasing design complexity. The accurate verification ability at the architectural level through a large set of the test programs and real world applications is a foundation for the next design step. In this paper, we describe how to verify a functional model on a real target system. The proposed methodology called virtual chip makes it possible not only to check the functional correctness on real systems, but also to explore design space by measuring the performance effectiveness of various architecture parameters under real applications. Experimental results show that functional models can be verified on real systems using complicated application programs. The proposed functional verification method is faster than HDL simulation and even comparable to emulation.